1. Field of the Invention
The invention relates to the enhancement of a breakdown voltage between drain and source in a MOSFET semiconductor device.
2. Description of the Related Art
A conventional MOSFET semiconductor device has been proposed in Japanese Unexamined Patent Publication No. 55-108773, and is illustrated in FIGS. 1A to 1C, in which FIG. 1B is a plan view illustrating a layout pattern of a conventional MOSFET semiconductor device, FIG. 1A is a common cross-sectional view taken along the lines A--A and B--B, and FIG. 1C is a plan view of a conventional MOSFET semiconductor device, showing an area in which an n-type drain region is formed.
As illustrated in FIG. 1A, a conventional MOSFET semiconductor device includes a p-type substrate 1 which is comprised of an n-type drain region 2, an n.sup.+ -type drain layer 3 located within the n-type drain region 2 and located at a surface of the p-type substrate 1, an n.sup.- -type drain region 5 located adjacent to the n-type drain region 2, a p-type top layer 6 located adjacent to both the n.sup.- -type drain region 5 and the n-type drain region 2, and located at a surface of the p-type substrate 1, an n.sup.+ -type source region 9 spaced away from the n.sup.- -type drain region 5 and located at a surface of the p-type substrate 1, and a p.sup.+ -type back gate 10 located adjacent to the n.sup.+ -type source region 9 and at a surface of the p-type substrate 1.
An insulating film 7 is formed on a surface of the p-type substrate 1, covering the p-type top layer 6, the n.sup.- -type drain region 5 and an exposed surface of the p-type substrate 1. On the insulating film 7 is formed a gate electrode 8 bridging over the n.sup.- -type drain region 5 and the n.sup.+ -type source region 9. The p-type substrate 1 is covered with an interlayer insulating film 12, on which there are formed a drain electrode 4 communicating to the n.sup.+ -type drain layer 3, and a source electrode 11 communicating to both the n.sup.+ -type source region 9 and the p.sup.+ -type back gate 10.
The n-type drain region 2 is formed so that the n-type drain region 2 is present beneath the entire p-type top layer 6, as indicated with hatching in FIG. 1C.
In the conventional MOSFET semiconductor device having the above mentioned structure, when a voltage is applied across the n.sup.+ -type drain layer 3 and both the n.sup.+ -type source region 9 and the p.sup.+ -type back gate 10, there is also a voltage applied across both the p-type substrate 1 and the p-type top layer 6 and both the n.sup.- -type drain region 5 and the n-type drain region 2, resulting in an expanded depletion layer in the n.sup.- -type drain region 5 and the n-type drain region 2.
In the conventional MOSFET semiconductor device, a layout pattern to be formed on a chip is designed to have a folded pattern in order to increase the density in an area of a chip. For example, as illustrated in FIG. 1B, a layout pattern constituted of the above mentioned regions 2, 5 and 9, layers 3 and 6, and p.sup.+ -type back gate 10 is comprised of elongated straight portions S running parallel to each other and a curved portion C, forming a radius around the end of the p+-type back gate 10 and n+-type source. A similar curve could be found near the terminus of a drain region, as shown (for example) in FIG. 5B.
It has been found that a breakdown voltage between the p-type top layer 6 and both the n-type drain region 2 and the p-type substrate 1, measured in proximity to the curved portion C when a voltage is applied across the drain electrode 4 and the source electrode 11, is lower than a breakdown voltage measured in the straight portions S in the same condition. The reason for this phenomenon is as follows.
A width of a depletion layer formed when a p-n junction is reverse biased is determined so that negative charges of electrons are balanced in absolute value with positive charges of holes within a diffusion layer. Consider a pattern having a straight elongated portion S and a curved portion C, as illustrated in FIG. 2.
The pattern is constituted of an n-type region and a p-type region that extend adjacent to and in parallel with each other in stepped-junction fashion. Suppose that an electron content of the n-type region is equal to a hole content of the p-type region. In the illustrated pattern, in order to accomplish the above mentioned condition that charges are equal in the p- and n-type regions, a width W1 of a depletion layer D1 formed in the p-type region has to be equal to a width W2 of a depletion layer D2 formed in the n-type region (W1=W2).
However, in order for the negative charges of electrons to be equal to the positive charges of holes in the curved portion C, a width W3 of a depletion layer D3 of the p-type region has to be smaller than a width W2 of a depletion layer D4 of the n-type region (W3&lt;W2=W1). Thus, the width W3 of the depletion layer D3 in the curved portion C is smaller than the width W1 of the depletion layer D1 in the straight portion S (W3&lt;W1), which means that the total width W.sub.c of a depletion layer in the curved portion C is smaller than the total width W.sub.s of a depletion layer in the straight portion S (W.sub.c &lt;W.sub.s). As a result, an electric field having greater intensity is applied to the depletion layer D3 formed in the p-type region in the curved portion C. Accordingly, semiconductor in the proximity to the curved portion C inevitably has a smaller breakdown voltage.
According to experiments, for instance, the straight elongated portion S can have a breakdown voltage of about 600 V, whereas the curved portion C can have a breakdown voltage of merely about 400 V. Thus, a breakdown voltage of an entire MOSFET semiconductor device is determined in accordance with a breakdown voltage of a curved portion. For instance, the MOSFET semiconductor device could have a breakdown voltage of about 400 V in the above mentioned case, rather than the more desirable 600 V.
U.S. Pat. No. 5,258,636 issued to Rumennik et al. on Nov. 2, 1993 has suggested a method of enhancing a breakdown voltage in a curved portion of a semiconductor device which is similar in structure to one disclosed in the above mentioned Japanese Unexamined Patent Publication No. 55-108773. However, it is impossible to form a channel in the curved portion in the device disclosed in U.S. Pat. No. 5,258,636, and hence there arises the unavoidable problem of increased resistance between a drain and a source when a MOSFET is turned on.
As has been explained, a breakdown voltage between a drain and a source is determined by the breakdown voltage in the vicinity of the curved portion C in a device having been suggested in Japanese Unexamined Patent Publication No. 55-108773. Thus, the problem is that a MOSFET semiconductor device has to have a smaller breakdown voltage than that of a device having no curved portions.
The method suggested in U.S. Pat. No. 5,258,636 has the unavoidable problem of increased drain to source resistance.